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V826516G04S 128 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 16M x 64
PRELIMINARY
CILETIV LESO M
Features
JEDEC 200 Pin DDR Unbuffered Small-Outline, Dual In-Line memory module (SODIMM); 16,777,216 x 64 bit organization. Utilizes High Performance 16M x 8 DDR SDRAM in TSOPII-66 Packages Single +2.5V ( 0.2V) Power Supply Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All Inputs, Outputs are SSTL-2 Compatible 4096 Refresh Cycles every 64 ms Serial Presence Detect (SPD) DDR SDRAM Performance
Component Used
tCK tAC Clock Frequency (max.) Clock Access Time CAS Latency = 2.5
Description
The V826516G04S memory module is organized 16,777,216 x 64 bits in a 200 pin memory module. The 16M x 64 memory module uses 8 Mosel-Vitelic 16M x 8 DDR SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
-7
143
-75
133
-8
125
Units
MHz
(PC266A) (PC266B) (PC200)
7
7.5
8
ns
Module Speed
A1 B0 B1 PC1600 (100MHz @ CL2) PC2100B (133MHz @ CL2.5) PC2100A (133MHz @ CL2)
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Part Number Information
V
MOSEL VITELIC MANUFACTURED
8
2
65
16
G
0
4
S
X
T
G - XX
SPEED A1 (100MHZ@CL2) B0 (133MHZ@CL2.5) B1 (133MHZ@CL2) LEAD FINISH G = GOLD
DDRSDRAM 2.5V WIDTH DEPTH 200 PIN Unbuffered SODIMM X8 COMPONENT REFRESH RATE 4K STTL 4 BANKS
COMPONENT PACKAGE, T = TSOP COMPONENT REV LEVEL
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Block Diagram
CS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 S
D0
D4
DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D1
DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D5
DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D2
DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
Clock Wiring Clock Input CK0/CK0 CK1/CK1 CK2/CK2
D6
SDRAMs 4 SDRAMs 4 SDRAMs NC
Serial PD SCL WP SDA A0 SA0 A1 SA1 A2 SA2
DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D3
DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS DM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7
S
D7
R=120 5%
Dram1 Dram2 Dram3 Dram4
Card Edge *Clock Net Wiring
BA0 - BA1 A0 - A13 RAS CAS CKE0 WE
BA0-BA1: DDR SDRAMs D0 - D7
VDDSPD
SPD D0 - D7 D0 - D7
A0-A13: DDR SDRAMs D0 - D7 VDD/VDDQ RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D7 VREF VSS VDDID
D0 - D7 D0 - D7 Strap: see Note 4
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ.
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Pin Configurations (Front Side/Back Side)
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 Front VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0 VSS
Key
Pin 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133
Front DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2 VDD CKE1 DU(A13) A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE S0 DU VSS DQ32 DQ33 VDD DQS4
Pin 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
Front DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 DQ58 DQ58 DQ59 VDD SDA SCL VDDSPD VDDID
Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66
Back VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS
Key
Pin 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134
Back DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/(RESET) VSS VSS VDD VDD CKE0 DU(BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS CAS S1 DU VSS DQ36 DQ37 VDD DM4
Pin 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
Back DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26
DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30
Notes:
* These pins are not used in this module.
Pin Names
Pin
A0~A11 BA0~BA1 DQ0~DQ63 DQS0~DQS7 CK0~CK2, CK0~CK2, CKE0 CS0 RAS CAS WE DM0~DM7
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Pin Description
Address Input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data - In Mask
Pin
VDD VDDQ VSS VREF VDDSPD SDA SCL SA0~2 VDDID NC
Pin Description
Power Supply (2.5V) Power Supply for DQS(2.5V) Ground Power Supply for Reference Serial EEPOM Power Supply (2.3V to 3.6V) Serial Data I/O Serial Clock Address in EEPROM VDD Identification Flag No Connection
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Serial Presence Detect Information
Bin Sort: A1 (PC1600 @ CL2) B0 (PC2100B @ CL2.5) B1 (PC2100A @ CL2)
Function Supported Byte #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Hex value A1 B0
80h 08h 07h 0Ch 0Ah 01h 40h 00h 04h
Function described
Defines # of Bytes written into serial memory at module manufacturer Total # of Bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly .........Data width of this assembly VDDQ and interface standard of this assembly DDR SDRAM cycle time at CAS Latency =2.5 DDR SDRAM Access time from clock at CL=2.5 DIMM configuration type(Non-parity, Parity, ECC) Refresh rate & type Primary DDR SDRAM width Error checking DDR SDRAM data width Minimum clock delay for back-to-back random column address DDR SDRAM device attributes : Burst lengths supported DDR SDRAM device attributes : # of banks on each DDR SDRAM DDR SDRAM device attributes : CAS Latency supported DDR SDRAM device attributes : CS Latency DDR SDRAM device attributes : WE Latency DDR SDRAM module attributes
A1
B0
128bytes 256bytes SDRAM DDR 12 10 1 Bank 64 bits SSTL 2.5V
B1
B1
8ns
7.5ns
7ns
80h 80h
75h 75h 00 80h 08h 00h 01h
70h 70h
0.8ns 0.75ns 0.70ns Non-parity, ECC 15.6us & Self refresh x8 x0 tCCD =1CLK 2,4,8 4 banks 2,2.5 0CLK 1CLK Unbuffered Diff Clock +/-0.2V voltage tolerance 10ns 10ns 7.5ns
16 17 18 19 20 21
0Eh 04h 0Ch 01h 02h 20h
22 23 24 25 26 27 28
DDR SDRAM device attributes : General DDR SDRAM cycle time at CL =2 DDR SDRAM Access time from clock at CL =2 DDR SDRAM cycle time at CL =1.5 DDR SDRAM Access time from clock at CL =1.5 Minimum row precharge time (=tRP) Minimum row activate to row active delay(=tRRD)
00h A0h 80h A0h 80h 00h 00h 50h 3Ch 50h 3Ch 48h 38h 75h 75h
0.8ns 0.80ns 0.75ns 20ns 15ns 20ns 15ns 18ns 14ns
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Serial Presence Detect Information (cont.)
Function Supported Byte #
29 30 31 32 33 34 35 36-40 41
Hex value A1
50h 32h
Function described
Minimum RAS to CAS delay(=tRCD ) Minimum active to precharge time(=tRAS) Module ROW density Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset information (may be used in future) SDRAM device minimum active to active/auto-refresh time (=tRC ) SDRAM device minimum active to autorefresh to active/auto-refresh time (=tRFC) SDRAM device maximum device cycle time (=tCK MAX) SDRAM device maximum skew between DQS and DQ signals (=tDQSQ) SDRAM device maximum read datahold skew factor (=tQHS) Superset information (may be used in future) SPD data revision code Checksum for Bytes 0 ~ 62 Manufacturer JEDEC ID code ....... Manufacturer JEDEC ID code Manufacturing location Module part number (ASCII) Manufacturer revison code (For PCB) Manufacturer revison code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial #
A1
20ns 50ns
B0
20ns 45ns 128MB
B1
18ns 45ns
B0
50h 2Dh 20h
B1
48h 2Dh
1.1ns 1.1ns 0.6ns 0.6ns
0.9ns 0.9ns 0.5ns 0.5ns -
0.9ns 0.9ns 0.5ns 0.5ns
B0h B0h 60h 60h
90h 90h 50h 50h 00h
90h 90h 50h 50h
70ns
65ns
60ns
46h
41h
3Ch
42
80ns
75ns
67ns
50h
4Bh
43h
43 44
12ns 0.6ns
12ns 0.5ns
12ns 0.5ns
30h 3Ch
30h 32h
30h 32h
45 46-61 62 63 64 65 -71 72 73-90 91 92 93 94 95~98
1ns
0.75ns -
0.75ns
A0h
75h 00h 00h
75h
Initial release Mosel Vitelic Mosel Vitelic BC
02 40h 00h 01h
A1
V826516G04S 0 0 Undefined Undefined 00 00 00h 00h
99~127 Manufacturer specific data (may be used in future) 128~255 Open for customer use
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DC Operating Conditions
(TA = 0 to 70C, Voltage referenced to VSS = 0V)
Parameter
Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage I/O Termination Voltage Reference Voltage Input Leakage Current Output Leakage Current Output High Current (VOUT = 1.95V) Output Low Current (VOUT = 0.35V)
Symbol
VDD VDDQ VIH VIL VTT VREF II IOz IOH IOL
Min
2.3 2.3 VREF + 0.15 -0.3 VREF - 0.04 1.15 -2 -5 -16.8 16.8
Typ.
2.5 2.5 VREF 1.25 -
Max
2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 1.35 2 5 -
Unit
V V V V V V A A mA mA
Note
1
2
3
Notes: 1. VDDQ must not exceed the level of VDD . 2. VIL (min) is acceptable -1.5V AC pulse width with 5ns of duration. 3. The value of VREF is approximately equal to 0.5VDDQ.
AC Operating Conditions
(TA = 0 to 70 C, Voltage referenced to VSS = 0V)
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs
Symbol
VIH(AC) VIL(AC) VID(AC) VIX(AC)
Min
VREF + 0.31
Max
Unit
V
Note
VREF - 0.31 0.7 0.5*VDDQ-0.2 VDDQ + 0.6 0.5*VDDQ+0.2
V V V 1 2
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
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(VDD = 2.5V, VDDQ = 2.5V, TA = 25C, f = 1MHz)
Parameter
Input capacitance (A0 ~ A11, BA0 ~ BA1, RAS, CAS, WE) Input capacitance (CKE0) Input capacitance (CS0) Input capacitance (CLK1, CLK2) Data & DQS input/output capacitance (DQ 0~DQ63) Input capacitance (DM0~DM8)
CILETIV LESO M
AC Operating Test Conditions (TA = 0 to 70C, Voltage referenced to VSS = 0V)
Parameter
Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (R S) Output Load Capacitance for Access Time Measurement (C L)
Value
VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30
Unit
V V V V V V V V/ns 3/4 3/4 pF
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
Symbol
CIN1 CIN2 CIN3 CIN4 COUT CIN5
Min
36 36 34 34 8 8
Max
45 45 42 38 9 9
Unit
pF pF pF pF pF pF
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DDR SDRAM IDD SPEC TABLE
B1(DDR266@CL=2) Symbol Typical
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A 800 1000 200 360 280 240 400 1360 1480 1480 16 8 2600
B0(DDR266@CL=2.5) Typical
800 1000 200 360 280 240 400 1360 1480 1480 16 8 2600
A1(DDR200@CL=2) Unit Notes Typical
640 800 160 320 240 200 320 1120 1200 1200 16 8 2120
Worst
880 1120 240 440 320 280 480 1600 1720 1720 16 8 3000
Worst
880 1120 240 440 320 280 480 1600 1720 1720 16 8 3000
Worst
720 920 200 360 280 240 400 1320 1360 1360 16 8 2480 mA mA mA mA mA mA mA mA mA mA 16 8 mA Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25' C 2. Worst Case : Vdd = 2.7V, T= 10' C 3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
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AC Characteristics (AC operating conditions unless otherwise noted)
(PC1600) Parameter
Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Last Data-In to Read Command Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time CAS Latency = 2.5 CAS Latency = 2 Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS tCH tCL tAC tDQSCK tDQSQ tQH tHP tIS tIH tIS tIH tIPW tDQSH tDQSL tDQSS tDS tDH tDIPW tRPRE tRPST
(PC2100B) Min
65 75 48 20 15 1 20 15 1 35 7.5 10 0.45 0.45 -0.75 -0.75 tHPmin -0.75ns tCH/L min 0.9 0.9 1.0 1.0 2.2 0.4 0.4 0.75 0.5 0.5 1.75 0.9 0.4
(PC2100A) Min
70 80 50 20 15 1 20 15 1 35 8 10 0.45 0.45 -0.8 -0.8 tHPmin -0.75ns tCH/L min 1.1 1.1 1.1 1.1 0.4 0.4 0.75 0.6 0.6 2 0.9 0.4
Symbol
tRC tRFC tRAS tRCD tRRD tCCD tRP tWR tDRL tDAL tCK
Min
60 67 45 18 14 1 18 15 1 35 7 7.5 0.45 0.45 -0.75 -0.75 tHPmin -0.75ns tCH/L min 0.9 0.9 1.0 1.0 2.2 0.4 0.4 0.75 0.5 0.5 1.75 0.9 0.4
Max
120K 12 12 0.55 0.55 0.75 0.75 0.5 -
Max
120K 12 12 0.55 0.55 0.75 0.75 0.5 -
Max
120K 12 12 0.55 0.55 0.8 0.8 0.6 -
Unit
ns ns ns ns ns CLK ns ns CLK ns ns ns CLK CLK ns ns ns ns
Note
1
Clock Half Period
-
-
-
ns
1
Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width Write DQS Low Level Width CLK to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time
0.6 0.6 1.25 1.1 0.6
0.6 0.6 1.25 1.1 0.6
0.6 0.6 1.25 1.1 0.6
ns ns ns ns ns CLK CLK CLK ns ns ns CLK CLK
2,3,5,6 2,3,5,6 2,4,5,6 2,4,5,6 6
7 7
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AC Characteristics (cont.)
(PC1600) Parameter
Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Power Down Exit Time Exit Self Refresh to Non-Read Command Exit Self Refresh to Read Command Average Periodic Refresh Interval
(PC2100B) Min
0 0.25 0.4 2 10 75 200 -
(PC2100A) Min
0 0.25 0.4 2 10 80 200 -
Symbol
tWPRES tWPREH tWPST tMRD tPDEX tXSNR tXSRD tREFI
Min
0 0.25 0.4 2 10 75 200 -
Max
0.6 15.6
Max
0.6 15.6
Max
0.6 15.6
Unit
CLK CLK CLK CLK ns ns CLK us
Note
8
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE. 3. For command/address input slew rate >=1.0V/ns 4. For command/address input slew rate >=0.5V/ns and <1.0V/ns 5. CK, CK slew rates are >=1.0V/ns 6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM 8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Absolute Maximum Ratings
Parameter
Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to V SS Output Short Circuit Current Power Dissipation Soldering Temperature * Time
Symbol
TA TSTG VIN , V OUT VDD VDDQ IOS PD TSOLDER
Rating
0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 8 260 * 10
Unit
C C V V V mA W C * Sec
Note: Operation at above absolute maximum rating can adversely affect device reliability
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0.24 (6.0)
1
39 41
199
0.086 2.15
0.456 11.40
0.07 (1.8) 0.098 2.45
2 40 42
0.17 (4.20) 0.096 (2.40)
Z
1.896 (47.40)
Y
200
0.150 Max (3.80 Max) (4.00 Min) (4.00 Min) 0.157 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 Min)
0.102 Min
0.79 (20.00)
2- 0.07 (1.80)
1.25 (31.75) 0.018 0.001 (0.45 0.03) 0.01 (0.25) 0.024 TYP (0.60 TYP)
CILETIV LESO M
Package Dimensions
Units : Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10)
Full R 2x
0.04 0.0039 (1.00 0.10)
Detail Z
Detail Y
Tolerances : .006(.15) unless otherwise specified
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Label Information
Module Density
MOSEL VITELIC
Part Number Criteria of PC2100 or PC1600
DIMM manufacture date code
V826516G04SXXX-XX 128MB CLXX PC2100U-2533-080-A XXXX-XXXXXXX Assembly in Taiwan
CAS Latency
PC2100 U - 2533 - 08 0 - A
UNBUFFERED DIMM CL = 2.5 (CLK) tRCD = 3 (CLK) tRP = 3 (CLK) Gerber file JEDEC SPD Revision 0
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U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WEST
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
CILETIV LESO M
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
SINGAPORE
10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013
UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516
JAPAN
ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402
GERMANY (CONTINENTAL EUROPE & ISRAEL)
BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
CENTRAL / EAST
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029
(c) Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
V826516G04S Rev. 1.5 March 2002
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